View NCN49599MNG_7923361.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2013 march, 2013 ? rev. p0 1 publication order number: ncn49599/d ncn49599 product preview power line carrier modem the ncn49599 is a powerful power line communication soc combining low power cortex m0 processor with a high precision analogue front end. based on a dual 4800 baud s ? fsk channel technology, it offers an ideal compromise between speed and robustness for operations in a harsh environment. it is functional compatible with its predecessor ncn49597, extending frequencies up to cenelec d band for use in applications such as e-metering, home automation and street lighting. the ncn49599 benefits for more than 10 years of field experience in emetering and delivers innovative features such as a smart synchronisation and automatic baud rate detection. fully reprogrammable, it also supports building automation standard or full custom protocol. the configurable gpios allow connecting peripherals such as lcd or metering ics. features ? power line carrier modem for 50 and 60 hz mains ? embedded 1.2 a highly linear 2 stage power amplifier with current limitation and thermal protection. ? embedded arm cortex m0 processor, programmable embedded software ? compliant with cenelec en 50065 ? 1 ? dual s ? fsk channel ? programmable carrier frequencies in cenelec a ? d band ? half duplex ? data rate selectable: 300 ? 600 ? 1200 ? 2400 ? 4800 baud (@ 50 hz) 360 ? 720 ? 1440 ? 2880 ? 5760 baud (@ 60 hz) ? repetition and smart synchronization algorithm boost the robustness of communication ? selectable uart/full duplex uart to application microcontroller ? sci port to application microcontroller ? sci baudrate selectable: 9.6 ? 19.2 ? 38.4 ? 115.2 kb ? power supply 3.3 v and 12 v ? junction temperature range: ? 40 c to +125 c ? these devices are pb ? free and are rohs compliant typical applications ? amr: automated remote meter reading ? in home display ? building automation ? solar power ? streetlight control ? transmission of alerts (fire, gas leak, water leak) this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. on e 3 arm see detailed ordering and shipping information in the package dimensions section on page 38 of this data sheet. ordering information xxxx = date code y = plant identifier zz = traceability code http://onsemi.com marking diagrams qfn56 8x8, 0.5p case 485cn ncn49599 0c599 ? 001 awlyywwg 1 56 56 1
ncn49599 http://onsemi.com 2 application application example figure 1. typical application for the ncn49599s ? fsk modem pc20130109.1 tx_out ncn49599 48 52 41 tx_enb alc_in zc_in ref_out rx_in rx_out 42 meter interface application controller txd rxd br0 br 1 26 27 32 t_req resb 35 34 37 43 25 44 24 47 46 45 vssa vss vdd vdda 3v3_a 3v3_ d 3v3_a a ? a_out b ? b_out a+ b+ 3v3_d 51 1 54, 55 50 2 +12 vcc 53 vee 3 6 7 +12 +12 +12 optional external flash sdo sdi sck csb 30 29 28 31 3v3_d enb 49 39 rlim vdd1v8 4 23 sen 33 ilim 5 xin 21 22 xout ext_clk_en 19 gpio bus jtag interface test 38 txd/pres 20 8, 9, 10, 11, 17, 18, 36 12, 13, 14, 15, 16 r 9 r 13 r 12 r 7 r 8 r 10 r 5 r 4 r 6 r 14 r 2 r 3 r 1 r 11 r 15 r 16 r 17 r 18 r 19 c 18 c 17 c 1 c 16 c 14 c 15 c 13 c 10 c 5 c 3 c 4 c 2 c 6 c 7 c 8 c 9 d 1 d 2 d 5 d 6 d 7 y 1 vdd vee vss 56 c 19 c 12 mains 1: 2 c 11 d 3 d 4 tr 1 u 1 3v3_d figure 1 shows an s ? fsk plc modem build around ncn49599. for synchronization the line frequency is coupled in via r15, a 1 m resistor. the schottky diode pair d 5 clamps the voltage within the input range of the zero cross detector. in the receive path a 2 nd order high pass filter blocks the mains frequency. the corner point defined by c 7 , c 8 , r 10 and r 11 . in the transmit path a 3 th order low pass filter build around the internal power operational amplifier suppresses the 2 nd and 3 rd harmonics to be in line with the cenelec en 50065 ? 1 specification. the filter components are tuned for a space and mark frequency of 63.3 and 74 khz respectively, typically for e ? metering in the cenelec a ? band. the output of the amplifier is coupled via a dc blocking capacitor c 10 to a 2:1 pulse transformer tr1. the secondary of this transformer is coupled to the mains via a high voltage capacitor c 11 . high energetic transients from the mains are clamped by the protection diode combination d 3 , d 4 together with d 1 , d 2 . because the mains is not galvanic isolated care needs to be taken when interfacing to a microcontroller or a pc! table 1. external components list and description component function ? remark typ value tolerance unit c 1 tx_out coupling capacitor 470 20 % nf c 2 low pass transmit filter 470 10 % pf c 3 low pass transmit filter 68 10 % pf c 4 low pass transmit filter 3 10 % pf c 5 low pass transmit filter 2,7 10 % nf c 6 , c 16 , c 17 , c 18 , c 19 decoupling block capacitor 100 ? 20 +80% nf c 7 , c 8 high pass receive filter 1 10 % nf c 9 , c 13 v ref_out ; v dd1v8 decoupling cap ? ceramic 10 ? 20 +80% f
ncn49599 http://onsemi.com 3 table 1. external components list and description component unit tolerance typ value function ? remark c 10 tx coupling cap; 1a rms ripple @ 70 khz 10 20% f c 11 high voltage coupling capacitor; 630 v 220 20% nf c 12 zero cross noise suppression 100 20% pf c 14 , c 15 x ? tal load capacitor 36 20% pf r 1 low pass receive filter 3,3 1% k r 2 low pass receive filter 8,2 1% k r 3 , r 7 , r 8 , r 9 , r 12, r 13 , r 18, r 19 low pass transmit and high pass receive filter; voltage bias ; pull up 10 1% k r 4 low pass transmit filter 3 1% k r 5 low pass transmit filter 1 1% k r 6 low pass transmit filter 1,6 1% k r 10 high pass receive filter 15 1% k r 11 high pass receive filter 30 1% k r 14 tx coupling resistor ; 0.5 w 0,47 1% r 15 zero cross coupling hiv 1 5% m r 16 current protection 5 1% k r 17 ilim led current 3,3 5% k d 1 , d 2 high current schottky clamp diodes mbra430 d 3 , d 4 unidirectional transient voltage suppressor p6smb6.8at3g d 5 double low current schottky clamp diode bas70 ? 04 d 6 ilim led indication (optional) led d 7 bidirectional transient voltage suppressor 1sma12ca y 1 x ? tall 48 mhz tr 1 2:1 coupling transformer u 1 plc modem ncn49599
ncn49599 http://onsemi.com 4 table 2. absolute maximum ratings rating symbol min max unit absolute max. power amplifier supply v cc_absm v ee ? 0.3 13.2 v absolute max. digital power supply v dd_absm v ss ? 0.3 3.9 v absolute max. analog power supply v dda_absm v ssa ? 0.3 3.9 v absolute max. difference between digital and analog power supply v dd ? v dda_absm ? 0.3 0.3 v absolute max. difference between digital and analog ground v ss ? v ssa_absm ? 0.3 0.3 v absolute max. difference between digital and power ground v ss ? v ee_absm ? 0.3 0.3 v non 5v safe pins: tx_out, alc_in, rx_in, rx_out, ref_out, zc_in, xin, xout, enb, tdo, tdi, tck, tms, trstb, test absolute maximum input for normal digital inputs and analog inputs v in_absm v ss ? 0.3 v dd + 0.3 v absolute maximum voltage at any output pin v out_absm v ss ? 0.3 v dd + 0.3 v 5v safe pins: tx_enb, txd, rxd, br0, br1, io0 .. io7, resb absolute maximum input for digital 5v safe inputs v 5vs_absm v ss ? 0.3 6.0 v absolute maximum voltage at 5v safe output pin v out5v_absm v ss ? 0.3 3.9 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. normal operating conditions operating ranges define the limits for functional operation and parametric characteristics of the device as described in the normal operating conditions section and for the reliability specifications as listed in detailed hardware description section. functionality outside these limits is not implied. total cumulative dwell time outside the normal power supply voltage range or the ambient temperature under bias, must be less than 0.1% of the useful life as defined in detailed hardware description section. table 3. operating ranges rating symbol min max unit power supply voltage range v dd 3.0 3.6 v power operational amplifier voltage range v cc 6.0 12.0 v junction temperature range t j ? 40 125 c ambient temperature range t a ? 40 85 c
ncn49599 http://onsemi.com 5 pin description qfn packaging figure 2. qfn pin ? out of ncn49599 (top view) txd/pres ncn49599 1 2 3 4 5 6 7 8 9 10 11 12 13 27 26 25 24 23 22 21 20 19 18 17 16 15 42 41 40 39 38 37 36 35 34 33 32 31 30 44 45 46 47 48 49 50 51 52 53 54 55 56 14 28 29 43 vee b_out2 b_out1 vcc a_out a ? a+ zc_in ref_out rx_in rx_out vssa tdi io6 io7 ext_clk_en xin xout vdd1v8 vss vdd txd rxd tms tdo io5 io4 io3 vss vdd ilim rlim vee b+ b ? sdo csb io2 sen br1 br0 io1 test tx_out alc_in res trst io0 tck sck sdi nc vdda tx_en en table 4. ncn49599qfn pin function description pin no. pin name i/o type description 1 b ? in a negative ( ? ) input of operational amplifier b 2 b+ in a positive (+) input of operational amplifier b 3, 56 vee p negative supply for power amplifiers a and b 4 rlim a output b current limit set resistor 5 ilim out d current limit logic flag 6, 25 vdd p 3.3v digital supply 7, 24 vss p digital ground 8..11, 17, 18, 32, 36 io0 .. io7 in/out d, 5v safe general purpose i/o?s 12 tdo out d, 5v safe test data output 13 tdi in d, 5v safe, pd test data input 14 tck in d, 5v safe, pd test clock 15 tms in d, 5v safe, pd test mode select 16 trstb in d, 5v safe, pd test reset bar (active low) 19 ext_clk_en in d, 5v safe external clock enable input 20 txd/pres out d, 5v safe output of transmitted data (txd) or pre_slot signal (pres) 21 xin in a xtal input (can be driven by an external clock)
ncn49599 http://onsemi.com 6 table 4. ncn49599qfn pin function description pin no. description type i/o pin name 22 xout out a xtal output (output floating when xin driven by external clock) 23 vdd1v8 p 1v8 regulator output. foresee a decoupling capacitor 26 txd out d, 5v safe, od sci transmit output 27 rxd in d, 5v safe sci receive input (schmitt trigger input) 28 sck out d, 5v safe spi interface external flash 29 sdi in d, 5v safe spi interface external flash (schmitt trigger input) 30 sdo out d, 5v safe spi interface external flash 31 csb in d, 5v safe spi interface external flash (schmitt trigger input) 33 sen in d, 5v safe, pd spi interface enable external flash 34 br1 in d, 5v safe sci baud rate selection 35 br0 in d, 5v safe sci baud rate selection 37 resb in d, 5v safe master reset bar (schmitt trigger input, active low) 38 test in d, 5v safe, pd hardware test enable (schmitt trigger input) 39 tx_enb out d, 5v safe, od tx enable (active low) 40 nc not connected pin. tie to gnd. 41 tx_out out a transmitter output 42 alc_in in a automatic level control input 43 vdda p 3.3v analog supply 44 vssa p analog ground 45 rx_out out a output of receiver low noise operational amplifier 46 rx_in in a positive input of receiver low noise operational amplifier 47 ref_out out a reference output for stabilization 48 zc_in in a 50/60 hz input for mains zero cross detection 49 enb in d enable / shutdown power amplifier (active low) 50 a+ in a positive (+) input of operational amplifier a 51 a ? in a negative ( ? ) input of operational amplifier a 52 a_out out a output of operational amplifier a 53 vcc p positive supply for power amplifiers a and b 54 b_out1 out a output of operational amplifier b 55 b_out2 out a output of operational amplifier b p: power pin 5v safe: io that support the presence of 5v on bus line a: analog pin out: output signal d: digital pin in: input signal pd: internal pull down resistor od: open drain output
ncn49599 http://onsemi.com 7 table 5. ncn49599qfn pin function description in rom mode* pin no. pin name i/o type description 11 io0/rx_data out d, 5v safe, od data reception indication (in rom mode) 32 io2/t_req in d, 5v safe transmit request input (in rom mode) 36 io1/crc out d, 5v safe, od correct frame crc indication (in rom mode) *rom mode: io0,io1 and io2 has predefined function when ncn49599 boots from rom detailed pin description vdda vdda is the positive analog supply pin. nominal voltage is 3.3 v. a ceramic decoupling capacitor c da = 100 nf must be placed between this pin and the vssa. connection path of this capacitance to the vssa on the pcb should be kept as short as possible in order to minimize the serial resistance. ref_out ref_out is the analog output pin which provides the voltage reference used by the a/d converter. this pin must be decoupled to the analog ground by a 1 f ceramic capacitance c dref . the connection path of this capacitor to the vssa on the pcb should be kept as short as possible in order to minimize the serial resistance. vssa vssa is the analog ground supply pin. vdd vdd is the 3.3 v digital supply pin. a ceramic decoupling capacitor c dd = 100 nf must be placed between this pin and the vss. connection path of this capacitance to the vss on the pcb should be kept as short as possible in order to minimize the serial resistance. vss vss is the digital ground supply pin. vdd1v8 this is an additional power supply pin to decouple an internal ldo regulator. the decoupling capacitor should be placed as close as possible to this output pin as illustrated in figure 3. vee vee is the ground of the power amplifier. it is important to foresee a separate power ground line to this connection able to conduct 1.2 a without significant voltage drop. a recommended layout is illustrated in figure 3. vcc vcc is the supply connection to the power amplifier. this connection should be able to conduct 1.2 a without significant voltage drop. a decoupling capacitor should be placed as close as possible to this power pin as illustrated in figure 3. rx_out rx_out is the output analog pin of the receiver low noise input op ? amp. this op ? amp is in a negative feedback configuration. figure 3: recommended layout of the placement of decoupling capacitors rx_in rx_in is the positive analog input pin of the receiver low noise input op ? amp. together with rx_out and ref_out, an active high pass filter is realized. this filter removes the main frequency (50 or 60 hz) from the received signal. the filter characteristics are determined by external capacitors and resistors. a typical application schematic can be found in paragraph 50/60 hz suppression filter. zc_in zc_in is the mains frequency analog input pin. the signal is used to detect the zero cross of the 50 or 60 hz sine wave. this information is used, after filtering with the internal pll, to synchronize frames with the mains frequency. in case of direct connection to the mains it is advised to use a series resistor of 1 m in combination with two external clamp diodes in order to limit the current flowing through the internal protection diodes. rx_data (in rom mode only) rx_data is a 5 v compliant open drain output. an external pull ? up resistor defines the logic high level as illustrated in figure 4. a typical value for the pull ? up resistance ?r? is 10 k . the signal on this output depends on the status of the data reception. if ncn49599 waits for
ncn49599 http://onsemi.com 8 configuration rx_data outputs a pulse train with a 10 hz frequency. after synchronization confirm time out rx_data = 0. if ncn49599 is searching for synchronization rx_data = 1. pc20090722. 2 v ssd +5v output r figure 4. representation of 5v safe output tdo, tdi, tck, tms, and trstb all these pins are part of the jtag bus interface. the jtag interface is used during production test of the ic and will not be described here. input pins (tdi, tck, tms, and trstb) contain internal pull ? down resistance. tdo is an output. when not used, the jtag interface pins may be left floating. txd/pres txd/pres is the output for either the transmitting data (tx_data) or a synchronization signal with the time ? slots (pre_slot). txd/pres. more information can be found in paragraph local port. xin xin is the analog input pin of the oscillator. it is connected to the interval oscillator inverter gain stage. the clock signal can be created either internally with the external crystal and two capacitors or by connecting an external clock signal to xin. for the internal generation case, the two external capacitors and crystal are placed as shown in figure 5. for the external clock connection, the signal is connected to xin and xout is left unused. figure 5. placement of the capacitors and crystal with clock signal generated internally xtal_in pc20120530.2 xtal_out c x v ssa c x 48 mhz ext_clk_e the crystal is a classical parallel resonance type with its fundamental frequency equal to 48 mhz. for a typical load capacitance c l = 18 pf specified by the manufacturer of the crystal, the value of c x = 36 pf. the crystal has to fulfill impedance characteristics specified in the ncn49599 data sheet. as an oscillator is sensitive and precise, it is advised to put the crystal as close as possible on the board and to ground the case. xout xout is the analog output pin of the oscillator. when the clock signal is provided from an external generator, this output must be floating. when working with a crystal, this pin cannot be used directly as clock output because no additional loading is allowed on the pin (limited voltage swing). ext_clk_e ext_clk_e allows the user to connect an external clock instead of using a quartz. when this pin pulled to vdd an external clock has to be applied to the xin pin. when ext_clk_e is connected to vss, the quartz oscillator is operational. txd txd is the digital output of the asynchronous serial communication (sci) unit. in half ? duplex transmission (when booting from rom) and in full ? duplex mode (booted from flash or after download over uart) it is used to realize the communication between the ncn49599 and the application microcontroller. the txd is an open drain io (5 v safe). external pull ? up resistances (typically 10 k ) are necessary to generate the 5 v level. see figure 4 for the circuit schematic. rxd this is the digital input of the asynchronous sci unit. it is used in both half ? duplex and full ? duplex transmission (see txd pin description). this pin supports a 5 v level. it is used to realize the communication between the ncn49599 and the application microcontroller. rxd is a 5 v safe input. t_req (in rom mode only) t_req is the transmission request input of the serial communication interface when used in half ? duplex mode. when pulled low its initiate a local communication from the application micro controller to ncn49599. t_req is a 5 v safe input. see also paragraph serial communication interface. br1, br0 br0 and br1 are digital input pins. they are used to select the baud rate (bits/second) of the serial communication interface unit in half ? duplex mode. the rate is defined according to table 29 br1, br0 baud rate. the values are taken into account after a reset, hardware or software. modification of the baud rate during function is not possible. br0 and br1 are 5 v safe.
ncn49599 http://onsemi.com 9 crc (in rom mode only) crc is a 5 v compliant open drain output. an external pull ? up resistor defines the logic high level as illustrated in figure 4. a typical value for this pull ? up resistance ?r? is 10 k . the signal on this output depends on the cyclic redundancy code result of the received frame. if the cyclic redundancy code is correct crc = h during the pause between two time slots. resb resb is a digital input pin. it is used to perform a hardware reset of the ncn49599. this pin supports a 5 v voltage level. the reset is active when the signal is low (0 v). test test is a digital input pin with internal pull down resistor used to enable the hardware test mode of the chip. when test is left open or forced to ground normal mode is enabled. when test is forced to vdd the hardware test mode is enabled. this mode is used during production test of the ic and will not be described here. test pin is not 5 v safe. tx_enb tx_enb is a digital output pin. it is low when the transmitter is activated. the signal is available to turn on the line driver. tx_enb is a 5 v safe with open drain output, hence a pull ? up resistance is necessary achieve the requested voltage level associated with a logical one. see also figure 4 for reference. tx_out tx_out is the analog output pin of the transmitter. the provided signal is the s ? fsk modulated frames. a filtering operation must be performed to reduce the second and third order harmonic distortion. for this purpose an active filter is suggested. see also paragraph transmitter output tx_out. alc_in alc_in is the automatic level control analog input pin. the signal is used to adjust the level of the transmitted signal. the signal level adaptation is based on the ac component. the dc level on the alc_in pin is fixed internally to 1.65 v. comparing the peak voltage of the ac signal with two internal thresholds does the adaptation of the gain. low threshold is fixed to 0.4 v. a value under this threshold will result in an increase of the gain. the high threshold is fixed to 0.6 v. a value over this threshold will result in a decrease of the gain. a serial capacitance is used to block the dc components. the level adaptation is performed during the transmission of the first two bits of a new frame. eight successive adaptations are performed. see also paragraph amplifier with automatic level control (alc). sck, sdi, sdo, csb these signals form the spi interface to an optional external flash. see reference 1. sen sen is the spi enable signal. when pulled low ncn49599 will boot from the internal program rom. when pulled high (connected to vdd) the spi interface is active and the ic will boot from the external flash. boot up sequences are described in more detail in reference 1. io0 .. io7 io0 to io7 are 8 general purpose input/output pins. when booting from rom (sen = vss) io0 .. io2 have predefined functions: rx_data, crc and t_req respectively. when booting from external flash the user have access to all 8 of them. more information can be found in reference 1. a ? , a+, a_out, b ? , b+, b_out1, b_out2 these are the interface pins to the 2 highly linear power operational amplifiers. op amp b is capable to drive 1.2 a. rlim rlim is the connection to the current limit set resistor defining the current protection level of power op amp b . connecting a 5 k resistor between rlim and vee sets the current limit to i limit = 1.2 a. ilim ilim is the current limitation flag. this digital output is logic high when the output current of op amp b i out_b > i limit . enb this digital input enables both power amplifiers a and b when enb is driven low. a logic high will shutdown the amplifiers and put the outputs a_out, b_out1 and b_out2 in tri ? state.
ncn49599 http://onsemi.com 10 electrical characteristics dc and ac characteristics oscillator: pin xin, xout in production the actual oscillation of the oscillator and duty cycle will not be tested. the production test will be based on the static parameters and the inversion from xin to xout in order to guarantee the functionality of the oscillator. table 6. oscillator parameter test conditions symbol min typ max unit crystal frequency (note 1) f clk ? 100 ppm 48 +100 ppm mhz duty cycle with quartz connected (note 1) 35 65 % start ? up time (note 1) t startup 15 ms load capacitance external crystal (note 1) c l 18 pf series resistance external crystal (note 1) r s 1 6 60 maximum capacitive load on xout xin used as clock input cl xout 15 pf low input threshold voltage xin used as clock input vil xout 0.3 v dd v high input threshold voltage xin used as clock input vih xout 0.7 v dd v low output voltage xin used as clock input, xout = 2 ma vol xout 0.3 v high input voltage xin used as clock input voh xout v dd ? 0.3 v 1. guaranteed by design. maximum allowed series loss resistance is 60
ncn49599 http://onsemi.com 11 zero cross detector and 50/60 hz pll: pin zc_in table 7. zero cross detector and 50/60 hz pll parameter test conditions symbol min typ max unit maximum peak input current imp zc_in ? 20 20 ma maximum average input current during 1 ms imavg zc_in ? 2 2 ma mains voltage (ms) range with protection resistor at zc_in v mains 90 550 v rising threshold level (note 2) vir zc_in 1.9 v falling threshold level (note 2) vif zc_in 0.85 v hysteresis (note 2) vhy zc_in 0.4 v lock range for 50 hz (note 3) mains_freq = 0 (50 hz) flock 50hz 45 55 hz lock range for 60 hz (note 3) mains_freq = 0 (60 hz) flock 60hz 54 66 hz lock time (note 3) mains_freq = 0 (50 hz) tlock 50hz 15 s lock time (note 3) mains_freq = 0 (60 hz) tlock 60hz 20 s frequency variation without going out of lock (note 3) mains_freq = 0 (50 hz) df 60hz 0.1 hz/s frequency variation without going out of lock (note 3) mains_freq = 0 (60 hz) df 50hz 0.1 hz/s jitter of chip_clk (note 3) jitter chip_clk ? 25 25 s 2. measured relative to vss 3. these parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be gua ranteed by the digital test patterns.
ncn49599 http://onsemi.com 12 transmitter external parameters: pin tx_out, alc_in, tx_enb to guarantee the transmitter external specifications the tx_clk frequency must be 12 mhz 100 ppm. table 8. transmitter external parameters parameter test conditions symbol min typ max unit maximum peak output level f tx_out = 23 khz f tx_out = 148.5 khz level control at max. output v tx_out 0.85 0.76 1.15 1.22 vp second order harmonic distortion f tx_out = 148.5 khz level control at max. output hd2 ? 55 db third order harmonic distortion f tx_out = 148.5 khz level control at max. output hd3 ? 57 db frequency accuracy of the gener- ated sine wave (notes 4 and 6) df tx_out 30 hz capacitive output load at pin tx_out (note 4) cl tx_out 20 pf resistive output load at pin tx_out rl tx_out 5 k turn off delay of tx_enb output (note 5) td tx_enb 0.25 0.5 ms automatic level control attenuation step alc step 2.9 3.1 db maximum attenuation alc range 20.3 21.7 db low threshold level on alc_in vtl alc_in 0.46 0.34 v high threshold level on alc_in vth alc_in 0.72 0.54 v input impedance of alc_in pin r alc_in 111 189 k power supply rejection ration of the transmitter section (note 7) (note 8) psrr tx_out 10 35 db 4. this parameter will not be tested in production. 5. this delay corresponds to the internal transmit path delay and will be defined during design. 6. taking into account the resolution of the dds and an accuracy of 100 ppm of the crystal. 7. a sinusoidal signal of 10 khz and 100 mvpp is injected between vdda and vssa. the digital ad converter generates an idle patt ern. the signal level at tx_out is measured to determine the parameter. 8. a sinusoidal signal of 50 hz and 100 mvpp is injected between vdda and vssa. the digital ad converter generates an idle patte rn. the signal level at tx_out is measured to determine the parameter. the lpf filter + amplifier must have a frequency characteristic between the limits listed below. the absolute output level depends on the operating condition. in production the measurement will be done for relative output levels where the 0 db reference value is measured at 50 khz with a signal amplitude of 100 mv. table 9. transmitter frequency characteristics frequency (khz) attenuation unit min max 10 ? 0.5 0.5 db 145.5 ? 1.3 0.5 db 195 ? 4.5 ? 1.5 db 245 ? 3.0 db 500 ? 18.0 db 1000 ? 36.0 db 2000 ? 50 db
ncn49599 http://onsemi.com 13 receiver external parameters: pin rx_in, rx_out, ref_out table 10. receiver external parameters parameter test conditions symbol min typ max unit input offset voltage 42 db agc gain = 42 db v offs_rx_in 5 mv input offset voltage 0 db agc gain = 0 db v offs_rx_in 50 mv max. peak input voltage (corres- ponding to 62.5% of the sd full scale) agc gain = 0 db (note 9) v max_rx_in 0.85 1.15 vp input referred noise of the analog receiver path agc gain = 42 db (notes 9 and 10) nf rx_in 150 nv/ hz input leakage current of receiver input i le_rx_in ? 1 1 a max. current delivered by ref_out i max_ref_out ? 300 300 ma power supply rejection ratio of the receiver input section agc gain = 42 db (note 11) psrr lpf_out 10 db agc gain = 42 db (note 12) 35 db agc gain step agc step 5.5 6.5 db agc range agc range 39.9 44.1 db analog ground reference output voltage v ref_out 1.52 1.78 v signal to noise ratio at 62.5 % of the sd full scale (notes 9 and 13) sn ad_out 54 db clipping level at the output of the gain stage (rx_out) v clip_agc_in 1.05 1.65 vp 9. input at rx_in, no other external components. 10. characterization data only. not tested in production. 11. a sinusoidal signal of 10 khz and 100 mvpp is injected between vdda and vssa. the signal level at the differential lpf_out a nd ref_out output is measured to determine the parameter. 12. a sinusoidal signal of 50 hz and 100 mvpp is injected between vdda and vssa. the signal level at the differential lpf_out ou tput is measured to determine the parameter. 13. these parameters will be tested in production with an input signal of 95 khz and 1 vp by reading out the digital samples at the point ad_out with the default settings of t_rx_mod[7], sdmod_typ, dec_typ, and cor_f_ena. the agc gain is switched to 0 db. the receive lpf filter + agc + low noise amplifier must have a frequency characteristic between the limits listed below. the absolute output level depends on the operating condition. table 11. receiver frequency characteristics frequency (khz) attenuation unit min max 10 ? 0.5 0.5 db 148.5 ? 1.3 0.5 db 195 ? 4.5 ? 2.0 db 245 ? 3.0 db 500 ? 18.0 db 1000 ? 36.0 db 2000 ? 50 db
ncn49599 http://onsemi.com 14 power amplifier parameters: pin a+, a ? , a_out, b+, b ? , bout1&2, vss, vee, enb table 12. power amplifier general parameters parameter test conditions symbol min typ max unit output shutdown time enb 0 1 60 ns output enable time enb 1 0 5 10 s quiescent current enb = 0 i q_en 20 40 ma enb = 1 i q_dis 140 200 a thermal shutdown (note 14) +150 +160 c recovery from thermal shutdown (note 14) +135 c 14. characterization data only. not tested in production. table 13. power amplifier external parameters op amp a parameter test conditions symbol min typ max unit input offset voltage v cc = +12 v, v ee = 0 v v os 3 10 mv offset vs power supply v cc = +6 v, v ee = 6 v psrr 25 150 v/v input bias current (note 15) i b 1 na input voltage noise density f = 1 khz, v in = gnd, bw = 131 khz (note 15) e n 250 nv/ hz common ? mode voltage range v cm v ee ? 0.1 v cc ? 3 v common ? mode rejection ratio v ee 0.1 v cm v cc 3 cmrr 70 85 db differential input impedance 0.2 | 1.5 g | pf common ? mode input impedance 0.2 | 3 g | pf open ? loop gain r l = 500 (note 15) 80 100 db gain bandwidth product gwp 80 mhz full power bandwidth g = +5, v out = 11 v pp (note 15) 0.2 1.5 mhz slew rate sr 60 v/ s total harmonic distortion + noise g = +1, r l = 500 , v o = 8 v pp , f = 1 khz, c in = 220 f, c out = 330 f thd+n 0.015 % g = +1, r l = 50 , v o = 8 v pp , f = 100 khz, c in = 220 f, c out = 330 f thd+n 0.023 % voltage output swing from rail v cc = +12 v, v ee = 0 v from positive rail il = ? 12 ma v oh 0.3 1 v from negative rail il = + 12 ma v ol 0.3 1 v short circuit current i sc 280 ma output impedance closed loop g = +4, f = 100 khz z 0 0.25 capacitive load drive c load 100 pf 15. characterization data only. not tested in production.
ncn49599 http://onsemi.com 15 table 14. power amplifier external parameters op amp b parameter test conditions symbol min typ max unit input offset voltage v cc = +12 v, v ee = 0 v v os 3 10 mv offset vs power supply v cc = +12 v, v ee = 0 v psrr 25 150 v/v input bias current (note 16) i b 1 na input voltage noise density f = 1 khz, v in = gnd, bw = 131 khz e n 125 nv/ hz common mode voltage range v cm v ee ? 0.1 v cc ? 3 v common mode rejection ratio v ee 0.1 v cm v cc 3 cmrr 70 85 db differential input impedance 0.2 | 11 g | pf common mode input impedance 0.2 | 22 g | pf open loop gain r l = 5 (note 16) 80 100 db gain bandwidth product gwp 60 mhz full power bandwidth g = +2, v out = 11 v pp (note 16) 200 400 khz slew rate sr 70 v/ s total harmonic distortion + noise g = +1, r l = 50 , v o = 8 v pp , f = 1 khz thd+n 0.015 % g = +1, r l = 50 , v o = 8 v pp , f = 100 khz thd+n 0.067 % voltage output swing from rail v cc = +12 v, v ee = 0 v from positive rail i out = ? 1.2 a @ t j = 25 c v oh 0.7 1 v i out = ? 1.0 a @ t j = 125 c v oh 0.7 1 v from negative rail i out = + 1.2 a @ t j = 25 c v oh 0.4 1 v i out = + 1.0 a @ t j = 125 c v oh 0.4 1 v short circuit current r lim = 5 k i sc 1.2 a output impedance closed loop g = +1, f = 100 khz enabled mode enb = 0 z 0 0.065 shutdown mode enb = 1 z 0 12 m capacitive load drive c load 500 nf 16. characterization data only. not tested in production. power ? on ? reset (por) table 15. power ? on ? reset parameter test conditions symbol min typ max unit por threshold v por 2.1 2.7 v power supply rise time 0 to 3v t rpor 1 ms digital outputs: tdo, clk_out table 16. digital outputs: tdo, clk_out parameter test conditions symbol min typ max unit low output voltage i xout = 3 ma v ol 0.4 v high output voltage i xout = ? 3 ma v oh 0.85 v dd v
ncn49599 http://onsemi.com 16 digital outputs with open drain: tx_enb, txd table 17. digital outputs with open drain: tx_enb, txd, rx_data, crc, t_req parameter test conditions symbol min typ max unit low output voltage i xout = 4 ma v ol 0.4 v digital inputs: br0, br1 table 18. digital inputs: br0, br1 parameter test conditions symbol min typ max unit low input level v il 0.2 v dd v high input level 0 to 3 v v ih 0.8 v dd v input leakage current i leak ? 10 10 a digital inputs with pull down: tdi, tms, tck, trstb, test table 19. digital inputs with pull down: tdi, tms, tck, trstb, test parameter test conditions symbol min typ max unit low input level v il 0.2 v dd v high input level v ih 0.8 v dd v pull down resistor (note 17) r pu 7 50 k 17. measured around a bias point of v dd /2. digital schmitt trigger inputs: rxd, resb table 20. digital schmitt trigger inputs: rxd, resb parameter test conditions symbol min typ max unit rising threshold level v t+ 0.80 v dd v falling threshold level v t ? 0.2 v dd v input leakage current i leak ? 10 10 a
ncn49599 http://onsemi.com 17 current consumption table 21. current consumption parameter test conditions symbol min typ max unit current consumption in receive mode current through v dd and v dda (note 18) i rx 60 ma current consumption in transmit mode current through v dd and v dda (note 18) i tx 60 ma current consumption when resb = 0 current through v dd and v dda (note 18) i reset 4 ma current consumption when enb = 0 quiescent current though v cc i q_en 20 40 ma current consumption when esnb = 1 quiescent current though v cc i q_hiz 120 150 a 18. f clk = 48 mhz. introduction general description the ncn49599 is a single chip half duplex s ? fsk modem dedicated to power line carrier (plc) data transmission on low ? or medium ? voltage power lines. the device of fers complete handling of the protocol layers from the physical up to the mac. ncn49599 complies with the cenelec emc standard en 50065 ? 1 and the iec 61334 ? 5 ? 1 standards. it operates from a 3.3 v and 12 v power supply and is interfaced to the power line by an integrated power amplifier and transformer. an internal pll is locked to the mains frequency and is used to synchronize the data transmission at data rates of 300, 600, 1200, 2400 and 4800 baud for a 50 hz mains frequency, or 360, 720, 1440, 2880 and 5760 baud for a 60 hz mains frequency. in both cases this corresponds to 3, 6, 12 or 24 data bits per half cycle of the mains period. s ? fsk is a modulation and demodulation technique that combines some of the advantages of a classical spread spectrum system (e.g. immunity against narrow band interferers) with the advantages of the classical fsk system (low complexity). the transmitter assigns the space frequency f s to ?data 0? and the mark frequency f m to ?data 1?. the difference between s ? fsk and the classical fsk lies in the fact that f s and f m are now placed far from each other, making their transmission quality independent from each other (the strengths of the small interferences and the signal attenuation are both independent at the two frequencies). the frequency pairs supported by the ncn49599 are in the range of 9 ? 150 khz with a typical separation of 10 khz. the conditioning and conversion of the signal is performed at the analog front ? end of the circuit. the further processing of the signal and the handling of the protocol is digital. at the back ? end side, the interface to the application is done through a serial interface. the digital processing of the signal is partitioned between hardwired blocks and a microprocessor block. the microprocessor is controlled by firmware. where timing is most critical, the functions are implemented with dedicated hardware. for the functions where the timing is less critical, typically the higher level functions, the circuit makes use of the arm microprocessor core. the processor runs dsp algorithms and, at the same time, handles the communication protocol. the communication protocol, in this application, contains the mac = medium access control layer. the program is stored in a masked rom. depending on the status of the sen input, after power on reset ncn49599 will boot from internal rom or external flash or over the serial communication interface. the working data necessary for the processing is stored in an internal ram. at the back ? end side the link to the application hardware is provided by a serial communication interface (sci). the sci is an easy to use serial interface, which allows communication between an external processor used for the application software and the ncn49599 modem. the sci works on two wires: txd and rxd. baud rate is programmed by setting 2 bits (br0, br1). because the low protocol layers are handled in the circuit, the ncn49599 provides an innovative architectural split. thanks to this, the user has the benefit of a higher level interface of the link to the plc medium. compared to an interface at the physical level, the ncn49599 allows faster development of applications. the user just needs to send the raw data to the ncn49599 and no longer has to take care of the protocol detail of the transmission over the specific medium. this last part represents usually 50% of the software development costs.
ncn49599 http://onsemi.com 18 minor user type major user type pc201111 12.2 spy application ncn49597 in monitor mode test application ncn49597 in test mode client application ncn49597 in master mode server application ncn49597 in slave mode server application ncn49597 in slave mode figure 6. application examples ncn49599 is intended to connect equipment using distribution line carrier (dlc) communication. it serves two major and two minor types of applications: ? major types: ? master or client: a master is a client to the data served by one or many slaves on the power line. it collects data from and controls the slave devices. a typical application is a concentrator system ? slave or server: a slave is a server of the data to the master. a typical application is an electricity meter equipped with a plc modem. ? minor type: ? spy or monitor: spy or monitor mode is used to only listen to the data that comes across the power line. only the physical layer frame correctness is checked. when the frame is correct, it is passed to the external processor. ? test mode: the software test mode is used to test the compliance of a plc modem conforms to cenelec. en 50065 ? 1 by a continuous broadcast of f s or f m .
ncn49599 http://onsemi.com 19 functional description the block diagram below represents the main functional units of the ncn49599: figure 7. s ? fsk modem ncn49599 block diagram communication controller arm risc core serial comm. interface local port test control por watchdog timer 1 & 2 interrupt control program/data ram program rom aaf agc a/d ref s ? fsk demodulator receiver (s ? fsk demodulator) clock and control zero crossing pll osc clock generator & timer transmit data & sine synthesizer d/a lp filter transmitter (s ? fsk modulator) rx_data resb jtag i /f test tx_enb tx_out alc_in rx_out rx_in ref_out zc_in xin xout vssa vssd ncn49599 pc20130109.2 from line coupler to application micro controller txd rxd t_req br0 br1 crc txd/pres 5 vdd 1v8 io[7:3] 5 spi i/f 4 ext_clk_e flash spi sen to external flash power amplifier b a tsd current protect vdda vddd b_out1 b_out2 en a+ a ? b+ b ? a_out vee ilim rlim vcc power amplifier the power amplifier block contains a class a/b, low distortion line driver. its design is optimized to accept a signal from the transmitter. the output stage is designed to drive up to 1.2 a peak into an isolation transformer or simple coil coupling to the mains. at output current of 1.2 a, the output voltage is guaranteed to swing within 1 v or less of either rail giving the user improved snr. the input stage contains an operational amplifier which can be configured as a unity gain follower buffer or used to provide the first stage of a 4 ? pole low pass filter. current protection is set with a single resistor, rlim, together with a current limit flag. thermal protection is set by a voltage level at the vwarn pin. the output stage goes into a high ? impedance state once the junction temperature has exceeded +150 c. transmitter the ncn49599 transmitter function block prepares the communication signal which will be sent on the transmission channel during the transmitting phase. this block is connected to a power amplifier which injects the output signal on the mains through a line ? coupler. receiver the analog signal coming from the line ? coupler is low pass filtered in order to avoid aliasing during the conversion. then the level of the signal is automatically adapted by an automatic gain control (agc) block. this operation maximizes the dynamic range of the incoming signal. the signal is then converted to its digital representation using sigma delta modulation. from then on, the processing of the data is done in a digital way. by using dedicated hardware, a direct quadrature demodulation is performed. the signal demodulated in the base band is then low pass filtered to reduce the noise and reject the image spectrum. clock and control according to the iec 61334 ? 5 ? 1 standard, the frame data is transmitted at the zero cross of the mains voltage. in order to recover the information at the zero cross, a zero cross detection of the mains is performed. a phase ? locked loop (pll) structure is used in order to allow a more reliable reconstruction of the synchronization. this pll permits as well a safer implementation of the ?repetition with credit? function (also known as chorus transmission). the clock generator makes use of a precise quartz oscillator master. the clock signals are then obtained by the use of a programmed division scheme. the support circuits are also contained in this block. the support circuits include the necessary blocks to supply the references voltages for the ad and da converters, the biasing currents and power supply sense cells to generate the right power off and startup conditions.
ncn49599 http://onsemi.com 20 48 bit @ 2400 baud 20 ms t pc20100609.1 figure 8. data stream is in sync with zero cross of the mains (example for 50 hz) communication controller the communication controller block includes the micro ? processor, its peripherals: ram, rom, uart, timer, and the power on reset. the processor uses the arm reduced instruction set computer (risc) architecture optimized for io handling. for most of the instructions, the machine is able to perform one instruction per clock cycle. the microcontroller contains the necessary hardware to implement interrupt mechanisms, timers and is able to perform byte multiplication over one instruction cycle. depending on the s tatus of the sen input, after power on reset ncn49599 will boot from internal rom, external flash or over the serial communication interface. booting from rom will make the modem work conform to the iec ? 61334 ? 5 standard. the ram contains the necessary space to store the working data. the back ? end interface is done through the serial communication interface block which works in half ? duplex or full ? duplex mode. this back ? end is used for data transmission with the application micro controller and for the definition of the modem configuration. local port the controller uses 3 output ports to inform about the actual status of the plc communication. rx_data indicates if receiving is in progress, or if ncn49599 is waiting for synchronization, or of it configures. crc indicates if the received frames are valid (crc = ok). txd/pres is the output for either the transmitting data (tx_data) or a synchronization signal with the time ? slots (pre_slot). serial communication interface when booting from rom the local communication is a half duplex asynchronous serial link using a receiving input (rxd) and a transmitting output (txd). the input port t_req is used to manage the local communication with the application micro controller and the baud rate can be selected depending on the status of two inputs br0, br1. these two inputs are taken in account after an ncn49599 reset. thus when the application micro controller wants to change the baud rate, it has to set the two inputs and then provoke a reset. when booting from flash or over the sci, the serial communication interface is full duplex. detailed hardware description clock and control according to the iec 61334 ? 5 ? 1 standard, the frame data is transmitted at the zero cross of the mains voltage. in order to recover the information at the zero cross, a zero cross detection of the mains is performed. a phase ? locked loop (pll) structure is used in order to allow a more reliable reconstruction of the synchronization. the output of this block is the clock signal chip_clk, 8 times over sampled with the bit rate. the oscillator makes use of precise 48 mhz quartz. this clock signal together with chip_clk is fed into the clock generator and time block. here several internal clock signals and timings are obtained by the use of a programmed division scheme.
ncn49599 http://onsemi.com 21 figure 9. clock and control block clock and control zero crossing pll clock generator & timer zc_in xin xout pc20120530.1 bit_ clk by te_ clk frame_clk pre_byte_clk pre_frame_clk pre_slot chip_clk ext_clk_e osc zero cross detector zc_in is the mains frequency analog input pin. the signal is used to detect the zero cross of the 50 or 60 hz sine wave. this information is used, after filtering with the internal pll, to synchronize frames with the mains frequency. in case of direct connection to the mains it is advised to use a series resistor of 1 m in combination with two external schottky clamp diodes in order to limit the current flowing through the internal protection diodes. from mains clock & control zc_in zerocross pll chip_clk debounce filter 3v3_a 1m pc2010608.1 100 pf bas70 ? 04 figure 10. zero cross detector with falling edge de ? bounce filter the zero cross detector output is logic zero when the input is lower than the falling threshold level and a logic one when the input is higher than the rising threshold level. the falling edges of the output of the zero cross detector are de ? bounced by a period between 0.5 ms and 1 ms. the rising edges are not de ? bounced.
ncn49599 http://onsemi.com 22 t 10 ms v mains zerocross t zcd vir zc _in pc20090620 .1 vif zc _in t debounce = 0,5 .. 1 ms figure 11. zero cross detector signals and timing (example for 50 hz) 50/60 hz pll the output of the zero cross detector is used as an input for a pll. the pll generates the clock chip_clk which is 8 times the bit rate and which is in phase with the rising edge crossings. the pll locks on the zero cross from negative to positive phase. the bit rate is always an even multiple of the mains frequency, so following combinations are possible: table 22. chip_clk in function of selected baud rate and mains frequency baud[2:0] mains_freq baudrate chip_clk 000 50 hz 300 2400 hz 001 600 4800 hz 010 1200 9600 hz 011 2400 19200 hz 100 4800 38400 hz 000 60 hz 360 2880 hz 001 720 5760 hz 010 1440 11520 hz 011 2880 23040 hz 100 5760 46080 hz in case no zero crossings are detected the pll freezes its internal timers in order to maintain the chip_clk timing.
ncn49599 http://onsemi.com 23 6 bit @ 300 baud t 10 ms v mains zerocross t zcd vir zc _in chip _clk pc 20090 619 .3 pll in lock start of physical preframe (*) *the start of the physical subframe is shifted back with r_zc_adjust[7:0] x 13 s = t zcd to compensate for the zero cross delay. figure 12. zero cross adjustment to compensate for zero cross delay (example for 50 hz) the phase difference between the zero cross of the mains and chip_clk can be tuned. this opens the possibility to compensate for external delay t zcd (e.g. opto coupler) and for the 1.9 v positive threshold vir zc_in of the zero cross detector. this is done by pre ? loading the pll counter with a number value stored in register r_zc_adjust[7:0]. the adjustment period or granularity is 13 s. the maximum adjustment is 255 x 13 s = 3.32 ms which corresponds with 1/6 th of the 50 hz mains sine period. table 23. zero cross delay compensation r_zc_adjust[7:0] compensation 0000 0000 0 s 0000 0001 13 s 0000 0010 26 s 0000 0011 39 s 1111 1111 3315 s oscillator the oscillator works with a standard parallel resonance crystal of 48 mhz. xin is the input to the oscillator inverter gain stage and xout is the output. figure 13. placement of the capacitors and crystal with clock signal generated internally xin pc20120530.2 xout c x v ssa c x 48 mhz ext_clk_e
ncn49599 http://onsemi.com 24 for correct functionality the external circuit illustrated in figure 13 must be connected to the oscillator pins. for a crystal requiring a parallel capacitance of 18 pf c x must be around 36 pf. (values of capacitors are indicative only and are given by the crystal manufacturer). to guarantee startup the series loss resistance of the crystal must be smaller than 60 . ext_clk_e should be strapped to v ssa . if an external clock of 48 mhz is used, this signal should be connected to xin and ext_clk_e needs to be pulled to v dd the oscillator output f clk = 48 mhz is the base frequency for the complete ic. the clock frequency for the arm f arm = f clk. the clock for the transmitter, f tx_clk is equal to f clk / 4 or 12 mhz. all the transmitter internal clock signals will be derived from f tx_clk . the clock for the receiver, f rx_clk is equal to f clk / 8 or 6 mhz. all the receiver internal clock signals will be derived from f rx_clk. clock generator and timer the chip_clk and f clk are used to generate a number of timing signals used for the synchronization and interrupt generation. the timing g eneration has a fixed repetition rate which corresponds to the length of a physical subframe. (see paragraph reference 1) the timing generator is the same for transmit and receive mode. when ncn49599 switches from receive to transmit and back from transmit to receive, the r_chip_cnt counter value is maintained. as a result all timing signals for receive and transmit have the same relative timing. the following timing signals are defined as: bit_clk 63 64 65 2871 2872 1 0 2879 2 3 4 5 6 7 8 9 chip_clk byte_clk frame_clk pre_frame_clk pre_byte_clk r_chip_cnt pre_slot pc20090619.1 start of the physical subframe figure 14. timing signals chip_clk : is the output of the pll and 8 times the bit rate on the physical interface. see also paragraph 50/60 hz pll . bit_clk : is active at counter values 0, 8, 16, .. 2872 and inactive at all other counter values. this signal is used to indicate the transmission of a new bit. byte_clk : is active at counter values 0, 64, 128, .. 2816 and inactive at all other counter values. this signal is used to indicate the transmission of a new byte. frame_clk : is active at counter values 0 and inactive at all other counter values. this signal is used to indicate the transmission or reception of a new frame. pre_byte_clk is a signal which is 8 chip_clk sooner than byte_clk. this signal is used as an interrupt for the internal microcontroller and indicates that a new byte for transmission must be generated. pre_frame_clk is a signal which is 8 chip_clk sooner than frame_clk. this signal is used as an interrupt for the internal microcontroller and indicates that a new frame will start at the next frame_clk. pre_slot is logic 1 between the rising edge of pre_frame_clk and the rising edge of frame_clk. this signal can be provided at the digital output pin
ncn49599 http://onsemi.com 25 txd/pres when r_conf[7] = 0 (see paragraph local port and t able 26, field r_conf_txd_pres_sel ) and can be used by the external host controller to synchronize its software with the frame_clk of ncn49599. transmitter path description (s ? fsk modulator) for the generation of the space and mark frequencies, the direct digital synthesis (dds) of the sine wave signals is performed under the control of the microprocessor. after a signal conditioning step, a digital to analog conversion is performed. as for the receive path, a sigma delta modulation technique is used. in the analog domain, the signal is low pass filtered, in order to remove the high frequency quantization noise, and passed to the automatic level controller (alc) block, where the level of the transmitted signal can be adjusted. the determination of the signal level is done through the sense circuitry. transmitter(s ? fsk modulator ) pc20091019.1 arm interface & control tx_out transmit data & sine synthesizer d/a lp filter alc control alc_in to receiver f mi f mq f si f sq tx_en figure 15. transmitter block diagram arm interface and control the interface with the arm consists in a 8 ? bit data registers r_tx_data, 2 control registers r_tx_ctrl and r_alc_ctrl, a flag tx_rxb defining transmit and receive and 2 16 ? bit wide frequency step registers r_fm and r_fs defining f m (mark frequency = data 1) and f s (space frequency = data 0). all these registers are memory mapped. some of them are for internal use only and cannot be accessed by the user. processing of the physical frame (preamble, mac address, crc) is done by the arm. sine wave generator a sine wave is generated with a direct digital synthesizer dds. the synthesizer generates in transmission mode a sine wave either for the space frequency (f s , data 0) or for the mark frequency (f m , data1). in reception the synthesizer generates the sine and cosine waves for the mixing process, f si , f sq , f mi , f mq (space and mark signals in phase and quadrature). the space and mark frequencies are defined in an individual step 16 bit wide register. table 24. fs and fm step registers arm register hard reset soft reset description r_fs[15:0] 0000h 0000h step register for the space frequency f s r_fm[15:0] 0000h 0000h step register for the mark frequency f m the space and mark frequency can be calculated as: ? f s = r_fs[15:0]_dec x f dds /2 18 ? f m = r_fm[15:0]_dec x f dds /2 18 or the content of both r_fs[15:0] and r_fm[15:0] are defined as: ? r_fs[15:0]_dec = round(2 18 x f s /f dds ) ? r_fm[15:0]_dec = round(2 18 x f m /f dds ) ? where f dds = 3 mhz is the direct digital synthesizer clock frequency.
ncn49599 http://onsemi.com 26 after a hard or soft reset or at the start of the transmission (when tx_rxb goes from 0 to 1) the phase accumulator must start at it?s 0 phase position, corresponding with a 0 v output level. when switching between f m and f s the phase accumulator must give a continuous phase and not restart from phase 0 when ncn49599 goes into receive mode (when tx_rxb goes from 1 to 0) the sine wave generator must make sure to complete the active sine period. the control logic for the transmitter generates a signal tx_enb to enable the integrated power amplifier. tx_enb is 1 when the ncn49599 is in receive mode. tx_enb is 0 when ncn49599is in transmit mode. when going from transmit to receive mode (tx_rxb goes from 1 to 0) the tx_enb signal is kept active for a short period of t dtx_enb . the control logic for the transmitter generates a signal tx_data which corresponds to the transmitted s ? fsk signal. when transmitting f m tx_data is logic 1. when transmitting f s tx_data is logic 0. when the transmitter is not enabled (tx_rxb = 0) tx_data goes to logic 1 at the next bit_clk. pc200 90610.1 tx_data tx_rxb t dtx_enb bit_clk tx_enb tx_out figure 16. tx_enb timing da converter a digital to analog converter converts the sine wave digital word to a pulse density modulated (pdm) signal. the pdm signal is converted to an analog signal with a first order switched capacitor filter. low pass filter a 3 rd order continuous time low pass filter in the transmit path filters the quantization noise and noise generated by the da converter. the typical corner frequency f ? 3db = 138 khz and is internally trimmed to compensate for process variation. this filter can be tuned to f ? 3db = 195 khz to allow operating in the d ? band as described in reference 1. amplifier with automatic level control (alc) the pin alc_in is used for level control of the transmitter output level. first peak detection is done. the peak value is compared to two thresholds levels: vtl alc_in and vth alc_in . the result of the peak detection is used to control the setting of the level of tx_out. the level of tx_out can be attenuated in 8 steps of 3 db typical. after hard or soft reset the level is set at minimum level (maximum attenuation) when going to reception mode (when tx_rxb goes from 1 to 0) the level is kept in memory so that the next transmit frame starts with the old level. the evaluation of the level is done during 1 chip_clk period. depending on the value of peak level on alc_in the attenuation is updated: ? vp alc_in < vtl alc : increase the level with one 6 db step ? vtl alc vp alc_in vth alc : don?t change the level ? vp alc_in > vth alc : decrease the level with one 6 db step the gain changes in the next chip_clk period. an evaluation phase and a level adjustment take 2 chip_clk periods. alc operation is enabled only during the first 16 chip_clk cycles after a hard or soft reset or after going into transmit mode. the automatic level control can be disabled by setting register r_alc_ctrl[3] = 1. in this case the transmitter output level is fixed to the programmed level in the register r_alc_ctrl[2:0]. see reference 1.
ncn49599 http://onsemi.com 27 table 25. fixed transmitter output attenuation alc_ctrl[2:0] attenuation 000 0 db 001 ? 3 db 010 ? 6 db 011 ? 9 db 100 ? 12 db 101 ? 15 db 110 ? 18 db 111 ? 21 db power amplifier the integrated power amplifier consists of 2 independent operational amplifiers. the first or input stage is designed to build a 2 nd order low pass filter or to be used as unity gain follower buffer. the second or power stage is a low distortion class a/b line driver able to deliver 1.2 a peak current with the output voltage guaranteed to swing within 1 v or less of either rail giving the user improved snr. current protection is set with a single resistor, r lim. the output stage goes into a high impedance state once the junction temperature has exceeded +150 c coupling and filtering because the complete analog part of the s ? fsk modulator inside ncn49599 is referenced to the analogue ground ref_out, and its output is dc coupled to the tx_out pin, a decoupling capacitor c 1 is needed when connecting it to the power amplifier. to suppress the second and third order harmonic of the generated s ? fsk signal it is recommended to use a 2 nd or 3 th order low pass filter. in figure 17 a mfb topology of a 3 th order filter is illustrated to be compliant with the european cenelec en 50056 ? 1 standard for signaling on low voltage electrical installations in the frequency range 3 khz to 148.5 khz. figure 17. power amplifier and filtering transmitter (s ? fsk modulator) pc20120831.2 arm interface & control tx_out lp filter tx_en to coupler c 1 r 1 c 2 r 2 r 3 c 3 power amplifier r 5 r 4 r 6 c 5 c 4 b ? b+ a ? a+ b_out1 a_out b_out2 en r 22 r 8 r 7 a a c 6 v cc
ncn49599 http://onsemi.com 28 noise and stability optimal stability and noise rejection will be achieved with power supply decoupling capacitors close to vcc. current protection the current protection is set by the r lim resistor. it limits the output both when sourcing and sinking current. once the protection is trigged the i lim flag will go logic high signaling the user to take any necessary action. when the current output recovers, the i lim flag will return to logic low. to guarantee correct operation it is recommended to set r lim = 5 k this ensures the current will not exceed 1.2 a causing damage. see also paragraph safe operating area. thermal protection in the event load conditions cause internal over heating, the amplifier will go into shutdown to prevent damage. thermal shutdown takes place at an internal junction temperature of approximately 160 c; the amplifier will recover to the enabled mode when the junction temperature cools back down to approximately 145 c. safe operating area the safe operating area (soa) of the power amplifier is defined by 3 parameters: ? the thermal resistance from junction to ambient rth j ? a ? the output current i_outb or i l ? the output voltage. v_outb or v l the thermal resistance from junction to ambient rth j ? a strongly depends on board design. r thja = 50 k/w in free air is a typical value which may be used even if ncn49599 is soldered on a pcb mounted in a small closed box, provided the transmission of frames are infrequent and widely spread in time. this typical value is also used in the generation of the curves plotted in figures 18 and 19. figure 18 shows the soa in function of output current i l and output voltage v l with the ambient temperature as independent parameter. the maximum allowed current is 800 ma rms. for that reason it is recommended to limit the output current by using r lim = 5 k . this current limitation is plotted as a horizontal line. the maximal output voltage is limited by v cc,max , v oh and v ol . this results in the straight line on the right hand side of the v l ? i l plot. the area below and left from these limitations is considered as safe. the relation between output voltage and current is the impedance as seen at the output of the power operational amplifier. constant impedance lines are represented by canted lines. figure 18. soa in v l ?il space (bottom left corner is safe) with r thja = 50 k/w although voltage ? versus ? current is the normal representation of safe operating area, a plc line driver can only control one of these variables: voltage and current are linked through the mains impedance. figure 19 displays exactly the same information as figure 18 but might be easier to work with. here constant current values are now represented as canted lines.
ncn49599 http://onsemi.com 29 figure 19. soa in z l ?v l space (bottom right corner is safe) receiver path description receiver block diagram the receiver takes in the analog signal from the line coupler, conditions it and demodulates it in a data ? stream to the communication controller. the operation mode and the baud rate are made according to the setting in r_conf, r_fs and r_fm. the receive signal is applied first to a high pass filter. therefore ncn49599 has a low noise operational amplifier at the input stage which can be used to make a high pass active filter to attenuate the mains frequency. this high pass filter output is followed by a gain stage which is used in an automatic gain control loop. this block also performs a single ended input to differential output conversion. this gain stage is followed by a continuous time low pass filter to limit the bandwidth. a 4 th order sigma delta converter converts the analog signal to digital samples. a quadrature demodulation for f s and f m is than performed by an internal dsp, as well the handling of the bits and the frames. rx_out rx_in ref_out pc20090610.2 low noise opamp ref 1,65 v to digital receiver (analog path) gain lpf 4th order ad from digital figure 20. analog path of the receiver
ncn49599 http://onsemi.com 30 pc20110610.3 abs value accu receiver (digital path) 1 st decimator noise shaper compen ? sator agc control from analog to gain f si f mq f sq sliding filter sliding filter sliding filter sliding filter quadrature demodulator f s f m 2 nd decimator 2 nd decimator 2 nd decimator 2 nd decimator i m q m i s q s f mi from transmitter f mq f si f sq figure 21. digital path of the receiver adc and quadrature demodulation 50/60 hz suppression filter ncn49599 receiver input provides a low noise input operational amplifier in a follower configuration which can be used to make a 50/60 hz suppression filter with a minimum number of external components. pin rx_in is the positive input and rx_out is the output of the input low noise operational amplifier. ref_out is the analog output pin which provides the voltage reference (1.65 v) used by the a/d converter. this pin must be decoupled from the analog ground by a 1 f ceramic capacitance (c dref ). it is not allowed to load this pin. pc20090722.1 c 1 r 1 c 2 r 2 c dref rx_out rx_in ref_out received signal v ssa low noise opamp ref 1,65 v to agc receiver (s ? fsk demodulator) 2 3 4 v in figure 22. external component connection for 50/60 hz suppression filter rx_in is the positive analog input pin of the receiver low noise input op ? amp. together with the output rx_out an active high pass filter is realized. this filter removes the main frequency (50 or 60 hz) from the received signal. the filter characteristics are determined by external capacitors and resistors. typical values are given in t able 26. for these values and after this filter, a typical attenuation of 85 db at 50 hz is obtained. figure 22 represents external components connection. in a typical application the coupling transformer in combination with a parallel capacitance forms a high pass filter with a typical attenuation of 60 db. the combined effect of the two filters decreases the voltage level of 230 vrms at the mains frequency well below the sensitivity of the ncn49599.
ncn49599 http://onsemi.com 31 t frequency (hz) 10 100 1k 10k 100k vin/vrx_out (db) ? 140 ? 100 ? 60 ? 20 20 figure 23. transfer function of 50 hz suppression circuit table 26. value of the resistors and capacitors component value unit c 1 1.5 nf c 2 1.5 nf c dref 1 f r 1 22 k r 2 11 k remark: the analog part of ncn49599 is referenced to the internal analog ground ref_out = 1.65 v (typical value). if the external circuitry works with a different analogue reference level one must be sure to place a decoupling capacitor. auto gain control (agc) the receiver path has a gain stage which is used for automatic gain control. the gain can be changed in 8 steps of 6 db. the control of the agc is done by a digital circuit which measures the signal level after the ad converter, and regulates the average signal in a window around a percentage of the full scale. the agc works in two cycles: a measurement cycle at the rising edge of the chip_clk and an update cycle starting at the next chip_clk. low noise anti aliasing filter the receiver has a 3 rd order continuous time low pass filter in the signal path. this filter is in fact the same block as in the transmit path which can be shared because ncn49599 works in half duplex mode. the typical corner frequency f ? 3db = 138 khz and is internally trimmed to compensate for process variation. a/d converter the output of the low pass filter is input for an analog 4 th order sigma ? delta converter. the dac reference levels are supplied from the reference block. the digital output of the converter is fed into a noise shaping circuit blocking the quantization noise from the band of interest, followed by a decimation and a compensation step. quadrature demodulator the quadrature demodulation block takes the ad signal and mixes it with the in ? phase and quadrature phase of the f s and f m carrier frequencies. after a low pass filter and rectification the mixer output signals are further processed in software. there the accumulation over a period of chip_clk is done which results in the discrimination of data 0 and data 1.
ncn49599 http://onsemi.com 32 bit sync at the transmit side the data ? stream is in sync and in phase with the zero crossing of the mains. the complex impedance of the power line together with propagation delay in the zero cross detector and loop delay in the rx ? filter circuitry will cause a shift between the physical transmitted bit and the received s ? fsk signal as illustrated in figure 24. mains transmitted bit stream bit delay transmission over the power line modulation bit 0 bit1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 t pc20101119 .1 figure 24. bit delay cause by transmission over a power line to compensate for this delay between physical and demodulated bit a synchro bit value is introduced. it shifts forward the hardware demodulating process up to seven chip clocks. see figure 25. bit 0 bit1 bit 2 chip_clk sbv[2:0] = 0 sbv[2:0] = 3 pc20101119 .2 figure 25. compensation for bit delay by shifting forward the start of the demodulating process the synchro bit value can be set using register sbv [2:0]. table 27. synchro bit value sbv[2:0] bit delay 000 0 chip_clk 001 1 chip_clk 010 2 chip_clk 011 3 chip_clk 100 4 chip_clk 101 5 chip_clk 110 6 chip_clk 111 7 chip_clk communication controller the communication controller block includes the arm cortex m0 32 bit risc processor, its peripherals: data and program ram, program rom, timers 1 and 2, interrupt control, spi interface to an optional external flash memory, test control, watchdog and power on reset (por), i/o ports and the serial communication interface (sci). the micro ? processor is programmed to handle the physical layer (chip synchronization), and the mac layer conform to iec 61334 ? 5 ? 1. the program is stored in a masked rom. depending on status of the sen input, after power on reset ncn49599 will boot from internal rom , external flash or over the serial interface. the ram contains the necessary space to store the program and the working data. the back ? end interface is done through the local port and serial communication interface block. this back ? end is used for data transmission with the application micro controller (containing the application layer for concentrator, power meter, or other functions) and for the definition of the modem configuration. more boot options and further details can be found in reference 1. the following section will give a brief overview of the functionality when boot from rom. more details can be found in reference 1.
ncn49599 http://onsemi.com 33 figure 26. communication controller communication controller arm risc core por watchdog timer 1 & 2 interrupt control program rom resb pc20 12053 0.4 from receiver to transmit flash spi serial comm. interface txd rxd t_req br0 br1 local port rx_data crc io[9:3] 5 txd/ pres test test control csb sdo sdi data / program ram sen local port the controller uses 3 output ports to inform the actual status of the plc communication. rx_data indicates if ncn49599 is waiting for its configuration, if it is in research of synchronization, or if it is receiving data. crc indicates if the received frames are valid: the cyclic redundancy code (crc) is correct. txd/pres is the output for either the transmitting data (tx_data) or a synchronization signal with the time ? slots (pre_slot). when booting from rom (sen = vss) io[9:3] have no function. these io?s can be addressed when booting from the external flash. see also reference 1. table 28. overview functionality local port port function value explanation remark rx_data data reception 10 hz waiting for configuration output is oscillating 0 after synchro confirm time ? out 1 research of synchronization crc crc ok 0 1 during the pause between 2 timeslots when a correct frame is received txd/pres tx_data 0 transmit of f s r_conf[7] = 1 1 transmit of f m pre_slot 0 see figure 14 r_conf[7] = 0 1 see figure 14 serial communication interface (sci) the serial communication interface allows asynchronous communication. it can communicate with a uart = universal asynchronous receiver t ransmitter, acia = asynchronous communication interface adapter and all other chips that employ standard asynchronous serial communication. the serial communication interface has following characteristics: ? half duplex. ? standard nrz format. ? start bit, 8 data bits and 1 stop bit. ? hardware programmable baud ? rate via br0 and br1 pins (9600, 19200, 38400 and 115200 baud). ? 0 ? 5 v levels with open drain for txd. ? 0 ? 5v levels for rxd and t_req.
ncn49599 http://onsemi.com 34 communication controller arm risc core pc 20120530.5 serial comm. interface txd rxd t_req br0 br1 local port rx_data crc io[9:3] 5 txd/pres ncn49597 application micro controller 3v3 _d figure 27. connection to the application microcontroller serial communication interface physical layer description the following pins control the serial communication interface. txd: transmit data output. it is the data output of the ncn49599 and the input of the application micro controller. rxd: receive data input. it is the data input of the ncn49599 and the output of the application micro controller. t_req: transmit request input request for data transmission received from the application micro controller br0, br1: baud rate selection inputs. these pins are externally strapped to a value or controlled by the external application micro controller. table 29. br1, br0 baud rates br1 br0 sci baud rate 0 0 115200 0 1 9600 1 0 19200 1 1 38400 t bit idle (mark) lsb msb idle(mark) t bit 8 data bits 1 character pc20080523.3 d0 start d1 d2 d3 d4 d5 d6 d7 stop figure 28. data format arbitration and transfer in order to avoid collisions between the data sent by the ncn49599 and the application micro controller, the ncn49599 is chosen as the transmitting controller. this means that when there is no local transfer, the ncn49599 can initiate a local communication without taking account of the application micro controller state. on the other hand, when the application micro controller wants to send data (using a local frame), it must first send a request for communication through the local input por t named t_req (transmitting request). then the ncn49599 answers with a status message.
ncn49599 http://onsemi.com 35 transfer from application micro controller to ncn49599 when the application micro controller wants to initiate a local transfer, it must pull down the t_req signal. the ncn49599 answers within the t poll delay with the status message in which the application micro controller can read if the communication channel is available. if the communication is possible, the application micro controller can start to send its local frame with in the t sr delay. it should pull up the t_req signal as soon as the first character (stx) has been sent. if the beginning of the local frame is not received before the t sr delay was issued, the ncn49599 ignores the local frame. at the end of the data reception sent by the application micro controller on the rxd line, the ncn49599 sends a byte on the txd line in order to inform about the status of the transmitting (=0x06) or (=0x15). remark: if the application micro controller only wants to know the state of the ncn49599, it has just to pull up the t_req signal after the reception of the status message. pc20080523 .5 t_req rxd txd statusmessage local frame from base micro ack t poll t ack t sr figure 29. transfer from application microcontroller to ncn49599 if the length and the checksum of the local frame are both correct, the ncn49599 acknowledges with an character. in other cases, it answers with a character. in case of response, or no acknowledgement from ncn49599 in the t ack time ? out, a complete sequence must be restarted to repeat the frame. transfer from ncn49599 to application micro controller when the ncn49599 wants to send a frame, it can directly send it without any previous request. pc20080523.6 t_req rxd txd nak local frame from ncn49599 local frame from ncn49599 ack t ack t wbc t ack t wbc local frame from ncn49599 figure 30. transfer from ncn49599 to application micro controller if the length and the checksum of the local frame are both correct, the application micro controller acknowledges with an character. in other cases, it answers with a character. in case of response from the application micro controller, the ncn49599 will repeat the frame only once after a delay corresponding to t wbc (wait before continue). a non response from the application micro controller or a framing error when an character is awaited is considered as an acknowledgment.
ncn49599 http://onsemi.com 36 character time ? out in reception the time between two consecutive characters in a local frame should not exceed t ic (time ? out inter character): pc20080523 .7 character character t ic t figure 31. character time ? out after this delay, the frame reception is finished. if the length and the checksum are both correct, the local frame is taken in account otherwise all previous characters are discarded. the time out inter character (t ic ) is set by default at 10ms after a reset. the time out inter character (t ic ) is modified by the bit 7 of repeater parameter in the configuration frame. see reference [1]: ? bit 7 = 1 ? > the t ic value is constant at 10 ms, ? bit 7 = 0 ? > the t ic value represents 5 characters depending on the communication speed (defined by two local input ports br0 and br1). table 30. serial communication time ? out values time ? out meaning value tpoll delay max. awaited by the base micro between the t_req pull down and the status message transmission (delay polling) 20 ms ts r delay max. awaited by the ncn49599 between the end of the status transmitting and the reception of the stx character in the base micro frame (delay status/reception) 200 ms tack delay max. awaited by either the ncn49599 or the base micro between the end of a transmitting and the reception of the ack or nak character sent by the other (delay ack). 40 ms twbc delay max. awaited by either the ncn49599 or the base micro between the end of a reception and the transmission of the next frame (delay waiting before continue). 5 ms tic delay max. awaited by either the ncn49599 or the base micro between two characters (delay inter characters) programmable with the bit 7 of repeater parameter in the configura- tion frame bit 7 = 1 10 ms bit 7 = 0 4800 baud 10 ms 9600 baud 5 ms 19200 baud 2.5 ms 38400 baud 1.25 ms watchdog the watchdog supervises the arm and in case the firmware doesn?t acknowledge at periodic times, a hard reset is generated. configuration registers a number of configuration registers can be accessed by the user by sending a writeconfig_request over the sci interface. see also reference [1]. a brief overview of the accessible configuration registers is given below: r_config register configures the ncn49599 in the correct mode. the r_config register is controlled by the embedded software and can be accessed via a writeconfig_request.
ncn49599 http://onsemi.com 37 table 31. r_conf[9:0] arm register hard reset soft reset description r_conf[7] 0 ? txd/pres_sel r_conf[5:3] 000 ? mode r_conf[2:1] 00 ? baudrate r_conf[0] 0 ? mains_freq where: txd/pres_sel: 0: txd/pres is pre_slot output pin 1: txd/pres is tx_data output pin mode: 000 : initialization 001 : master mode 010 : slave mode 011 : reserved 1xx : test mode baudrate: 00: 6 data bits per mains period = 300 baud @ 50 hz 01: 12 data bits per mains period = 600 baud @ 50 hz 10: 24 data bits per mains period = 1200 baud @ 50 hz 11: 48 data bits per mains period = 2400 baud @ 50 hz mains_freq: 0: 50 hz 1: 60 hz r_fs and r_fm step registers are defining the space and mark frequency. explanation on the values can be found in paragraph sine wave generator. this register can be accessed via a writeconfig_request. table 32. fs and fm step registers arm register hard reset soft reset description r_fs[15:0] 0000h 0000h step register for the space frequency f s r_fm[15:0] 0000h 0000h step register for the mark frequency f m r_zc_adjust register defines the value which is pre ? loaded in the pll counter . this is used to fine tune the phase dif ference between chip_clk and the ? to + zero cross of the mains. explanation on the values can be found in paragraph 50/60 hz pll. table 33. zc_adjust registers arm register hard reset soft reset description r_zc_adjust[7:0] 02h 02h fine tuning of phase difference between chip_clk and rising edge of mains zero cross r_alc_ctrl register enables or disables the automatic level control. in case alc is disabled the attenuation of the tx output driver is fixed according to the value in r_alc_ctrl[2:0]. explanation on the attenuation values can be found in paragraph amplifier with automatic level control. table 34. alc_ctrl registers arm register hard reset soft reset description r_alc_ctrl[3:0] 00h 00h control register for the automatic level control where: r_alc_ctrl[3]: 0: automatic level control is enabled 1: automatic level control is disabled and attenuation is fixed r_alc_ctrl[2:0]: fixed attenuation value
ncn49599 http://onsemi.com 38 table 35. fixed transmitter output attenuation alc_ctrl[2:0] attenuation 000 0 db 001 ? 3 db 010 ? 6 db 011 ? 9 db 100 ? 12 db 101 ? 15 db 110 ? 18 db 111 ? 21 db reset and low power ncn49599 has 2 reset modes: hard reset and soft reset. the hard reset initializes the complete ic (hardware and arm) excluding the data ram for the arm. this makes sure that start ? up of hardware and arm is guaranteed. a hard reset is active when pin resb = 0 or when the power supply v dd < v por (see table 15). when switching on the power supply the output of the crystal oscillator is disable until a few 1000 clock pulses have been detected, this to enable the oscillator to start up. the soft reset initializes part of the hardware. the soft reset is activated when going into initialization mode for the durati on of maximum 1 chip_clk. initialization mode is entered by r_conf[5:3] = 000. the concept of ncn49599 has a number of provisions to have low power consumption. when working in transmit mode the analogue receiver path and most of the digital receive parts are disabled. when working in receive mode the analog transmitter and most if the digital transmit parts, except for the sine generation, are disabled. when the pin resb = 0 the power consumption is minimal. only a limited power is necessary to maintain the bias of a minimum number of analog functions and the oscillator cell. reference in this document references are made to: 1. design manual ncn49599 http://www.onsemi.com 2. en 50065 ? 1: signaling on low ? voltage electrical installations in the frequency range 3 khz to 148.5 khz http://connect.nen.nl/~/preview.aspx?artfile=4257 28&rnr=66840 3. erdf ? cpt ? linky ? spec ? fonc ? cpl version v1.0 linky plc profile functional specification http://www.erdfdistribution.fr/medias/linky/erd f ? cpt ? linky ? spec ? fonc ? cpl.pdf 4. dlms ua 1000 ? 2 ed. 7.0 dlms/cosem architecture and protocols http://www.dlms.com/documentation/dlmsuacolou redbookspasswordprotectedarea/index.html 5. iec 61334 ? 5 ? 1 lower layer s ? fsk profile. http://webstore.iec.ch/preview/info_iec61334 ? 5 ? 1 %7bed2.0%7db.pdf 6. iec 61334 ? 5 ? 1 lower layer s ? fsk profile. http://webstore.iec.ch/preview/info_iec61334 ? 5 ? 1 %7bed2.0%7db.pdf table 36. ordering information device temperature range package shipping ? NCN49599MNG ? 40 c ? 125 c qfn ? 56 (pb ? free) tube ncn49599mntwg ? 40 c ? 125 c qfn ? 56 (pb ? free) tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncn49599 http://onsemi.com 39 package dimensions qfn56 8x8, 0.5p case 485cn issue o seating 0.15 c (a3) a a1 b 1 56 56x l 56x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c e notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.25mm from the terminal tip 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 8.00 bsc d2 6.50 6.70 e 8.00 bsc 6.70 e2 6.50 e 0.50 bsc l 0.30 0.50 k 0.20 ??? plane mounting footprint* l1 0.05 0.15 note 4 e/2 e2 d2 note 3 detail b l1 detail a l alternate constructions l dimensions: millimeters 8.30 6.74 6.74 0.50 0.60 0.32 56x 56x pitch 8.30 pkg outline 1 recommended a m 0.10 b c m 0.05 c a m 0.10 b c a m 0.10 b c *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncn49599/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of NCN49599MNG

	To Download NCN49599MNG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .